Logic circuits with clock-controlled decoupling stages that are connected by clock-signal lines to a clock generating circuit are referred to as dynamic or synchronized logic circuits. In such circuits, the processing speed depends not on the signal propagation delay through the individual logic stages, but on the period of a clock signal. Within a single clock unit, several logic stages may cooperate as one functional circuit unit, where the processing within this circuit unit is asynchronous in accordance with the technology-dependent propagation delay of the individual logic stages. The clock-synchronized input and output of data in the individual logic stages or circuit units is controlled by decoupling stages, with the design of the clock system and the decoupling stages ensuring that no data collision with other stages occurs at the input or output. The clock system switches the decoupling stages into an "on" state and an "off" state and ensures that the decoupling stages associated with logic stages or circuit units to be separated, particularly with logic stages or circuit units connected in series, are never simultaneously on.
A known clock system which achieves the desired synchronization in connection with clock-controlled decoupling stages is the nonoverlapping two-phase clock. The nonoverlapping clocks can be derived, for example, from a higher-frequency clock signal by applying logic operations. They may also be formed from an equal-frequency clock signal by evaluating the unavoidable propagation delays of logic stages. In a fundamental publication by Carver Mead and Lynn Conway, "Introduction to VLSI Systems", Addison-Wesley Publishing Company, 1980, pages 229 to 233, particularly FIG. 7, 6(a) on page 229, an exemplary circuit is described for generating the nonoverlapping two-phase clock by the second method. The nonoverlapping portion can be further enlarged, and thus made less sensitive to circuit or clock tolerances, by adding inverters in the respective clock lines. Such a two-phase clock generator is shown in FIG. 1 of U.S. Pat. No. 5,047,659 entitled "Non-Overlapping Two-Phase Clock Generator Utilizing Floating Inverters", issued on Sep. 10, 1991 to M. Ulrich and assigned to the assignee herein.
"Elektronikpraxis", No. 1, January 1983, page 91 describes a clock-generating circuit with an interlock circuit which switches the clock-signal line into a defined level state by means of an interlocking signal. The interlock circuit serves to ensure that upon turn-off and restart, only complete pulses are delivered as clock signals, so that the mark/space ratio remains accurately defined.
Especially suitable clock-controlled decoupling stages are logic stages with additional switch devices for the clock signals. The simplest example is a clocked inverter consisting of four series-connected p- and n-channel transistors. Another decoupling stage is a transfer gate formed from a parallel-connected n- and p-channel transistor pair which is connected into the signal line as an electronic series switch. Other clock-controlled decoupling stages are familiar to those skilled in the an, as are clock systems with more than two clock phases.
Clock-controlled decoupling stages generally suffer from the drawback that if the clock signal fails to appear, the outputs of the decoupling stages slowly change to a floating voltage state which, depending on the leakage currents present, lies more or less in the middle between the positive and negative supply potentials. The logic stages or circuit units connected to the output of the decoupling stage then see a drive potential which is not defined in the normal operating state with a 1 or 0 level, and which is traversed only briefly during a signal change. This may result in undefined operating states and cause disturbances which occur during the then clock-free operating state or only later when the clocks are turned on again. It is particularly disturbing if the logic stages or circuit units connected to the output of the decoupling stage are placed by this floating drive potential in a condition in which a steady-state shunt current flows between the positive and negative supply sources. This shunt current either does not occur in the normal sequence of operations, or it occurs only very briefly during the switching edges when the drive signal changes from one logic state to the other. Thus, a steady-state shunt current precipitated by the clock-signal failing to appear, may then become so large that the associated, possibly internal, voltage supply will be overloaded.
By turning off the clocks, at least in portions of an integrated circuit, a current reduction is to be effected through a standby mode in which the major part of the circuit remains in a current-saving, i.e., clock-free, state. Turning off the clocks is also advantageous upon turn-on of the supply voltage when the clock does not set in until the supply voltage is sufficiently high. If an uncontrolled shunt current flows during this starting phase, the start will be delayed and the supply-voltage source may, in the worst case, stick at a low voltage value due to overloading. In addition, upon turn-on, an internal configuration, known as "power-on reset", is generally initiated which should be completed prior to the onset of the clocks.
It is therefore the object of the present invention to provide a circuit for clock-controlled logic circuits which prevents the shunt-current paths in the logic circuit in the clock-free condition.